Silicon Labs /Series1 /EFM32GG12B /EFM32GG12B410F1024GQ64 /PDM /CFG0

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Interpret as CFG0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SECOND)FORDER 0 (ONE)NUMCH 0 (RIGHT16)DATAFORMAT 0 (ONE)FIFODVL 0 (STEREOMODECH01)STEREOMODECH01 0 (STEREOMODECH23)STEREOMODECH23 0 (CH0CLKPOL)CH0CLKPOL 0 (CH1CLKPOL)CH1CLKPOL 0 (CH2CLKPOL)CH2CLKPOL 0 (CH3CLKPOL)CH3CLKPOL

DATAFORMAT=RIGHT16, FORDER=SECOND, NUMCH=ONE, FIFODVL=ONE

Description

PDM Core Configuration Register0

Fields

FORDER

Filter order

0 (SECOND): Second order filter.

1 (THIRD): Third order filter.

2 (FOURTH): Fourth order filter.

3 (FIFTH): Fifth order filter.

NUMCH

Number of Channels

0 (ONE): Only one Channel.

1 (TWO): Two Channels.

2 (THREE): Three Channels.

3 (FOUR): Four Channels.

DATAFORMAT

Filter output format

0 (RIGHT16): Right aligned 16-bit, left bits are sign extended.

1 (DOUBLE16): Pack two 16-bit samples into one 32-bit word.

2 (RIGHT24): Right aligned 24bit, left bits are sign extended.

3 (FULL32BIT): 32 bit data.

4 (LEFT16): Left aligned 16-bit, right bits are zeros.

5 (LEFT24): Left aligned 24-bit, right bits are zeros.

6 (RAW32BIT): RAW 32 bit data from Integrator.

FIFODVL

Data Valid level in FIFO

0 (ONE): Atleast one word.

1 (TWO): Two words.

2 (THREE): Three words.

3 (FOUR): Four words.

STEREOMODECH01

Stereo mode CH01

STEREOMODECH23

Stereo mode CH23

CH0CLKPOL

CH0 CLK Polarity

CH1CLKPOL

CH1 CLK Polarity

CH2CLKPOL

CH2 CLK Polarity

CH3CLKPOL

CH3 CLK Polarity

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